1. Field of the Invention
The present invention relates to a circuit for generating horizontal and vertical synchronization signals for internal use based on horizontal and vertical synchronization signals included in a television signal (TV signal).
2. Description of the Related Art
In a device for reproducing a TV signal, such as a television receiver, a video player, or the like, reliable synchronization is achieved by separating horizontal and vertical synchronization signals from an externally supplied TV signal, internally generating horizontal and vertical synchronization signals synchronized with the obtained horizontal and vertical synchronization signals, and using these internally generated horizontal and vertical synchronization signals.
FIG. 4 shows a structure of a related art synchronization signal generating circuit. An external TV signal is supplied to a synchronization separation circuit 10, in which a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC are separated from the TV signal. The horizontal synchronization signal HSYNC is supplied to a VCO/AFC circuit 12. This VCO/AFC circuit internally has a PLL (phase-locked loop) circuit, and generates a 4 MHz internal clock synchronized with the supplied horizontal synchronization signal HSYNC. This internal clock is then supplied to an H countdown circuit 14. The H countdown circuit 14 counts clocks of the internal clock, and generates a horizontal synchronization signal HS for internal use.
Here, a signal having a period of a half of one horizontal period is necessary in a vertical retrace period, and the H countdown circuit 14 generates a 2×FH signal which is a signal having a frequency of twice that of one horizontal period. Then, this 2×FH signal is supplied to a V countdown circuit 16. The vertical synchronization signal VSYNC separated in the synchronization separation circuit 10 is also supplied to this V countdown circuit 16, the timing of this vertical synchronization signal VSYNC (for example, a fall time of the vertical synchronization signal VSYNC which has “H” level normally) is synchronized with the 2×FH signal, and a normalized vertical synchronization signal VS is obtained.
The horizontal synchronization signal HS and the vertical synchronization signal VS thus obtained are used to control the display timing of a display.
A process for synchronization signals for video signals is described in, for example, Japanese Patent Laid-Open Publication No. Hei 09-154082.
Here, the horizontal and vertical synchronization signals HS and VS generated in the manner described above are perfectly synchronized, as in the original TV signal.
However, in a video signal processing circuit, when the timing of these signals is shifted to some extent, vertical jitter on an OSD (on-screen display) may occur due to change in number of horizontal counts within a vertical period in a next-stage circuit or the like, depending on whether HS comes before or after VS.